1. Field of the Invention
The present invention generally relates to integrated circuit design. More particularly, the invention relates to techniques for cross-mapping integrated circuit design formats.
2. Background Information
The ubiquitous presence of integrated circuits (“ICs”) in almost every electronic device is testament to their importance in today's society. An integral part of producing ICs is “failure analysis,” which is the determination of why product failure is occurring. For example, if an IC has a current leakage path on an input/output pin, the pin may be deemed defective, but the actual root cause of the leakage current may still be unknown. Furthermore, it can be extremely difficult to determine exactly what is causing the defective IC to fail, especially when the IC has been packaged. IC technology trends only exacerbate this problem, as the number of transistors contained in each successive generation of ICs doubles approximately every eighteen months and more routing layers are required to connect tightly packed circuit elements. Methods for determining the root cause of the defective ICs may involve many levels of abstraction. For example, testing a packaged IC would entail high level of abstraction, whereas testing different points on the surface of the IC would entail a more detailed level of abstraction. Thus, the particular analysis used to determine the root cause of the problem is commensurate with the nature of the failure since some problems may be determined by testing the packaged IC, and other problems would require testing at the surface of the IC.
The basic functional testing of a packaged IC may be as simple as applying a voltage to the power pins, observing the level of current drawn by the packaged IC and checking that the current falls within specified limits. On the other hand, it may be necessary to test the operation of a specific circuit element (e.g., a single transistor) while the IC is operating, which, can be quite cumbersome when the IC is packaged in a “flip-chip” package because physical access to desired points on the IC via traditional probes is not possible. FIGS. 1A-1B help to illustrate this problem.
Referring now to FIG. 1A, an IC 10 is shown with circuits 11 integrated thereon. The IC 10 has circuitry 11 integrated on its frontside 10A, and includes bonding pads 12, which are used to make connections between the IC 10 and pins 14 of a package 16, which encapsulates the IC 10. The arrangement shown in FIG. 1A represents a top down view of a non-flip-chip configuration with the top of the package 16 removed so as to expose IC 10. In testing a non-flip-chip packaged IC such as the one shown in FIG. 1A, it is sometimes necessary to use a micro-mechanical probe 18 to perturb the states of individual transistors (i.e., toggling between “on” and “off” states) that are part of the circuitry 11. Because the IC 10 has been encapsulated in the package 16, the top layer of the package 16 is removed and access to the circuitry on the frontside 10A of the IC is then possible using the micro-mechanical probe 18. The micro-mechanical probe 18 has a needle like tip, (which can be on Me order of 1 μm) which is placed on the metal wires that couple the terminals of the desired transistor to other electrical devices. This procedure works relatively well when the frontside 10A of the IC 10 is accessible for probing with the mechanical probe 18, as seen in FIG. 1A.
However, packaging methods exist that orient the IC with the frontside 10A (which contains the circuitry) facing down. This is called “flip-chip” packaging. FIG. 1B shows a cross sectional view of a flip-chip package encapsulating IC 10, with its frontside 10A facing down and making connection between the bonding pads 12 and each pin 14 of the package 16. In this arrangement, access to the frontside 10A of the IC 10 cannot be gained by removing the top 19 of the packaging, as this would only yield access to its backside 10B, which does not contain any circuitry. Furthermore, the pins 14 of the flip-chip package 16 are in the form of conductive metal balls that span across the bottom of the package 16, so simply removing the bottom of the packaging to gain access to the circuitry with a micro-mechanical probe is impossible without completely removing the IC 10 from the flip-chip package 16, which is impractical.
One technique used in testing specific circuit elements that are not physically accessible with traditional probes uses an optical microscope/probe such as that described in, “Novel Failure Analysis Techniques Using Photon Probing With a Scanning Optical Microscope,” by E. I. Cole Jr. et al., which is incorporated herein by reference. In general this technique uses an optical probe that produces infrared light to perturb the state of individual circuit elements (i.e., altering a transistor's state from “on” to “off,” or vice versa) without actually making physical contact with the frontside of the IC. In order to accommodate the wavelengths of light used in the optical probe, the probe is directly applied to the backside of the IC, which, in a flip-chip arrangement, requires that the top of the flip-chip package be removed so as to expose the backside of the IC 10 to the light from the optical probe. Nevertheless, although the ability to probe any desired point is satisfied using an optical microscope/probe, finding the desired point in the IC to direct the probe to can still be like finding a needle in a haystack because physical access to the frontside of the IC is not available for viewing and navigating the optical probe. In addition, although the optical probe is capable of producing an image of the IC through the backside, often this image is not detailed enough to use in navigating the IC while looking for the desired probe point. This problem is only exacerbated by the millions of devices integrated in today's ICs, and thus, navigating the optical probe from an imprecise image can make it difficult to locate and probe the desired point.
In order to effectively use the optical probe, the desired point that needs to be perturbed is first found on the computer-automated drawing (“CAD”) representation of the IC. This CAD representation of the IC depicts the arrangement of the various metal and polysilicon materials used in actually building the IC in the fabrication facilities (or “fabs”), and is a reproduction of what is seen when viewing the IC through a microscope. Therefore the CAD representation serves as a good “road map” for finding a desired point on the actual IC that is being tested. For example, the actual fabricated IC can be on the order of 9 mm2, while the CAD representation can be printed as large as desired (e.g., 2 m2). Further, the CAD representation is computer based making it easier to track the connectivity of electrical devices in determining the point of interest and generate the coordinates of that point. However, correlating between the point of interest on the CAD representation or “road map” and the actual IC in a non-flip-chip arrangement can be difficult because of the density of the electrical devices, and can be even more difficult in a flip-chip packaging arrangement because of the imprecise image obtained from the optical probe as described above.
In addition to encountering problems, With optical probing arrangements, navigating through the various integrated structures in an IC using other probing methods can be problematic also. For example, invasive probing techniques using fine probing needles (e.g., on the order of 1 μm) may not be able to probe down to desired probe points on the IC because of interference from adjacent integrated structures, such as metal routing layers. This can be especially problematic in high-density areas of the IC, and becomes more problematic with each successive version of ICs as more routing layers are used. Thus, a need exists for an effective mechanism to direct any probe to a desired point in on an IC with minimal interference from adjacent structures.